1. Field of the Invention
The present invention relates to a power supply device which supplies electric power to an inductive load such as a motor.
2. Description of the Background Art
FIG. 10 is a diagram of the schematic configuration of a representative power supply device 1 according to the background art. The power supply device 1 has an output semiconductor element Q1 provided between a power supply line VCC and an output terminal OUT. A positive power supply voltage Vcc is supplied from a power supply BAT to the power supply line VCC. An inductive load RL such as a motor is connected to the output terminal OUT. Incidentally, the output semiconductor element Q1 consists of an insulated-gate type semiconductor element such as a power metal-oxide-semiconductor field-effect transistor (MOS-FET) or an insulated-gate bipolar transistor (IGBT) which can switch high electric power.
A gate voltage of the output semiconductor element Q1 is controlled by a drive circuit 3 provided in a control circuit 2 which is, for example, implemented as an integrated circuit. Thus, the output semiconductor element Q1 is driven and switched to control electric power supplied to the inductive load RL. The control circuit 2 imports a control signal, which is, for example, given from a microcomputer MC through an input terminal IN, to a logic circuit 4, in which a gate control signal for the output semiconductor element Q1 is generated.
Here, the logic circuit 4 receives an output of an overvoltage detection circuit 5, an output of a load release detection circuit 6 and an output of an overcurrent detection circuit 7 to control the generation of the gate control signal. The overvoltage detection circuit 5 monitors the power supply voltage Vcc. The load release detection circuit 6 monitors a voltage of the output terminal OUT. The overcurrent detection circuit 7 is configured to monitor a current flowing into the output semiconductor element Q1 from an output of a current detection semiconductor element Q2. For example, the current detection semiconductor element Q2 consists of an MOS-FET and is provided in parallel with the output semiconductor element Q1. Incidentally, the reference numeral 8 designates an internal power supply circuit which is incorporated into the control circuit 2 so that an internal power supply required for operating the control circuit 2 can be generated from the power supply voltage Vcc.
The control circuit 2 level-shifts the gate control signal, which is generated in the logic circuit 4, through the drive circuit 3 and applies the level-shifted gate control signal to a gate of the output semiconductor element Q1. Based on the gate control signal, the output semiconductor element Q1 is driven and switched. Incidentally, the gate control signal is also applied to a gate of the current detection semiconductor element Q2. Thus, the output semiconductor element Q1 and the current detection semiconductor element Q2 turn ON/OFF in linkage with each other.
When the output semiconductor element Q1 turns off, a counter electromotive force caused by an inductance component of the inductive load RL is generated in the inductive load RL. A negative voltage surge derived from the counter electromotive force is applied to the output terminal OUT. Incidentally, when the negative voltage surge exceeds a breakdown withstand voltage of the output semiconductor element Q1, the output semiconductor element Q1 breaks down. Then, the output semiconductor element Q1 deteriorates due to a breakdown current flowing into the output semiconductor element Q1. Therefore, there is a fear that the output semiconductor element Q1 may be thermally destructed.
In order to prevent such a problem, for example, a clamp circuit 9 is provided between the power supply line VCC, to which the power source voltage Vcc is supplied, and the gate of the output semiconductor element Q1, as shown in FIG. 10. The clamp circuit 9 is constituted, for example, by a Zener diode ZD and a diode D which are connected in series. The clamp circuit 9 serves for clamping the negative voltage surge applied to the output terminal OUT with reference to the power supply voltage Vcc. The clamp circuit 9 which clamps the negative voltage surge applied from the inductive load RL in this manner to protect the output semiconductor element Q1 has been introduced in detail, for example, in JP-A-2007-28747, JP-A-2006-148323, JP-A-2009-130949, etc.
Incidentally, when the clamp circuit 9 operates due to the negative voltage surge, a drain-source voltage of the output semiconductor element Q1 reaches the sum of a clamp voltage of the clamp circuit 9 and a threshold voltage of the output semiconductor element Q1, for example, as disclosed in paragraph [0007] of JP-A-2007-28747.
Assume that the output semiconductor element Q1 performs switching operation at the highest rated voltage. In this case, a clamp voltage which is almost as high as the highest rated voltage of the output semiconductor element Q1 is required in the clamp circuit 9 when the negative voltage surge is clamped with reference to the power supply voltage Vcc as described above. Such a high clamp voltage is intended to prevent the output semiconductor element Q1 from turning on in error due to a damp surge. Incidentally, the damp surge means a positive voltage surge applied to the power supply line VCC of the power supply device 1 when a terminal of the power supply BAT is detached from an alternator of a car in the case where, for example, the power supply device 1 is applied to the car.
In the case where, for example, the highest rated voltage of the output semiconductor element Q1 is 50V, a clamp voltage (withstand voltage) of about 50V is required in the diodes constituting the clamp circuit 9. Accordingly, when the clamp voltage set by the clamp circuit 9 is set at 50V with reference to the power supply voltage Vcc as shown in FIG. 11, the negative voltage surge applied to the output terminal OUT, from which, for example, an output voltage Vout can be obtained, can be clamped at −38V if the threshold voltage of the output semiconductor element Q1 is neglected.
Incidentally, FIG. 11 shows the relation between an output current Iout of the output semiconductor element Q1 and the voltage Vout of the output terminal OUT in the power supply device 1 from which an output voltage Vout of 12V can be obtained when the output semiconductor element Q1 turns ON. On the assumption that, for example, a variation in characteristics of the Zener diode ZD and the diode D constituting the clamp circuit 9 is 10% in this case, the clamp voltage may vary in the range of from 45V to 55V. In addition, when the clamp voltage is high, clamp resistance (which will be described later) during clamp operation of the clamp circuit 9 is reduced. Therefore, there also arises a problem that required characteristics of the output semiconductor element Q1 or the diodes constituting the clamp circuit 9 become strict to thereby adversely affect the cost.